
#define SET_ETHER_ADDR(a0_0,a0_1,a0_2,a0_3,a0_4,a0_5,a1_0,a1_1,a1_2,a1_3,a1_4,a1_5) \
  *R_NETWORK_SA_0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24); \
  *R_NETWORK_SA_1 = a0_4 | (a0_5 << 8) | (a1_0 << 16) | (a1_1 << 24); \
  *R_NETWORK_SA_2 = a1_2 | (a1_3 << 8) | (a1_4 << 16) | (a1_5 << 24);

#define TX_CTRL_EOP \
(IO_STATE(DMA_DESCR, intr, disable) |\
 IO_STATE(DMA_DESCR, wait, enable)  |\
 IO_STATE(DMA_DESCR, eop,  enable)  |\
 IO_STATE(DMA_DESCR, eol,  enable))
     
#define TX_CTRL \
     (IO_STATE(DMA_DESCR, intr, disable) |\
      IO_STATE(DMA_DESCR, wait, disable) |\
      IO_STATE(DMA_DESCR, eop,  disable) |\
      IO_STATE(DMA_DESCR, eol,  disable))
     









 



